The present invention relates to a Gray code counter that counts a clock signal and outputs a Gray code corresponding to a counted value of the clock signal.
The Gray code is a kind of binary representation, and is called a reflected binary code, in which the hamming distance of two adjacent numbers is designed to be 1 as shown in Table 1 of FIG. 7.
When the Gray code is applied to the output signal for a counter, for example, that outputs a value sequentially increasing by 1 at a time synchronously with the clock signal, signal variations during the up counting are limited to only one bit, and noises during the variations are limited accordingly, which is a notable feature of the Gray code. A general binary counter has a possibility to output an incorrect value momentarily during signal variations, due to a delay time difference between the signals of each bit; however, the Gray code counter does not have such a possibility, thus facilitating to design a circuit pattern, which is another feature.
FIG. 2 is a circuit diagram of a conventional Gray code counter, which is disclosed in the Japanese Published Unexamined Patent Application No. Hei 6-53818.
The Gray code counter includes a holding circuit 1 composed of plural D type flip-flops (hereunder, referred to as “DFF”) that hold signals DO through D3 supplied to the inputs of the holding circuit 1 synchronously with a clock signal CLK, and output them as output signals Q0 through Q3, and a logic circuit 2 that handles the output signals from the holding circuit 1 as the values of the Gray code, generates signals of the Gray code corresponding to the values larger by 1 than these, and outputs the result as the signals DO through D3.
The logic circuit 2 is configured to function as the up counter of the Gray code by making a complicated combination of logic gates, such as an exclusive logic sum gate (hereunder, “EOR”), logic sum gate (hereunder, “OR”), logic product gate (hereunder, “AND”), inverter (hereunder, “INV”), and so forth.
In the Gray code counter, when the clock signal CLK is given, the signals D0 through D3 that have been generated by the logic circuit 2 are held by the holding circuit 1 synchronously with the clock signal CLK, which are outputted as the output signals Q0 through Q3.
Inverted signals /Q0 through /Q3 of the output signals Q0 through Q3 outputted from the holding circuit 1 are also inputted to the logic circuit 2. The logic circuit 2 generates the Gray code corresponding to values lager by 1 than the values of the Gray code having been given by the holding circuit 1, and outputs the result as the signals D0 through D3.
And, when the next clock signal CLK is given, the signals D0 through D3 that have been generated by the logic circuit 2 are held by the holding circuit 1 synchronously with the clock signal CLK, which are outputted as the output signals Q0 through Q3. Thereby, the Gray code counter is able to output the Gray code that sequentially counts up synchronously with the clock signal CLK.
However, in the conventional Gray code counter, as shown by the logic circuit 2 in FIG. 2, there is a lack of regularity in the configuration of the logic gates that generates the signals D0 through D3 on the basis of the inverted signals /Q0 through /Q3 given by the holding circuit 1. Therefore, if there is a need to design a Gray code counter having an arbitrary bit-number (especially, multiple bits), a new logic gate configuration to comply with a desired bit number will have to be designed. Accordingly, as the bit number increases, the circuit design requires more time and the circuit configuration becomes more complicated, so that the pattern of the integrated circuit cannot be simplified, which presents a problem to be solved.